Bug found

[vancaho]

I found a bug in cpu.py:

    CPU_SUB_REGISTERS = {
        # main register name, shift, mask
        'al': ('rax', 0, 0xff),
        'bl': ('rbx', 0, 0xff),
        'cl': ('rcx', 0, 0xff),
        'dl': ('rdx', 0, 0xff),
        'ah': ('rax', 8, 0xff),
        'bh': ('rbx', 8, 0xff),
        'ch': ('rcx', 8, 0xff),
        'dh': ('rdx', 8, 0xff),
        'ax': ('rax', 0, 0xffff),
        'bx': ('rbx', 0, 0xffff),
        'cx': ('rcx', 0, 0xffff),
        'dx': ('rdx', 0, 0xffff),
        'eax': ('rax', 32, None),
        'ebx': ('rbx', 32, None),
        'ecx': ('rcx', 32, None),
        'edx': ('rdx', 32, None),
    }

here the shift and mask for eax, ebx, ecx, edx is wrong, the correct version should be:"

    CPU_SUB_REGISTERS = {
        # main register name, shift, mask
        'al': ('rax', 0, 0xff),
        'bl': ('rbx', 0, 0xff),
        'cl': ('rcx', 0, 0xff),
        'dl': ('rdx', 0, 0xff),
        'ah': ('rax', 8, 0xff),
        'bh': ('rbx', 8, 0xff),
        'ch': ('rcx', 8, 0xff),
        'dh': ('rdx', 8, 0xff),
        'ax': ('rax', 0, 0xffff),
        'bx': ('rbx', 0, 0xffff),
        'cx': ('rcx', 0, 0xffff),
        'dx': ('rdx', 0, 0xffff),
        'eax': ('rax', 0, 0xffffffff),
        'ebx': ('rbx', 0, 0xffffffff),
        'ecx': ('rcx', 0, 0xffffffff),
        'edx': ('rdx', 0, 0xffffffff),
    }

[vstinner]

Please provide a pull request. I no longer actively maintain this project.