Update DSR1 B200 FP4 SGLang config with low-latency search space

[RohitNagraj]

Restructures the aggregate dsr1-fp4-b200-sglang search space into low-latency lanes:

• 1k/1k: TP4/EP1 for conc 1–32, TP4/EP4 for conc 64–256.
• 8k/1k: TP4/EP1 for conc 1–32, TP4/EP4 with DP-attention for conc 64–256.
• Drops the TP8/EP8 single-concurrency points.

Config-only change — benchmarks/single_node/fixed_seq_len/dsr1_fp4_b200.sh already supports the TP4/EP1 and DP-attention lanes, so no script change is needed.

[github-actions]

Thanks for the contribution! For vLLM & SGLang, please ensure that your recipes is similar to the official vLLM recipes and/or the SGLang cookbook

• https://docs.sglang.io/cookbook/intro
• https://recipes.vllm.ai/

If it is not, please create a PR first before we can merge your single node PR into the master branch. Let's ensure that the documentation is first class such that the entire ML community can benefit from your hard work! Thank you

• https://github.com/vllm-project/recipes
• https://github.com/sgl-project/sglang/tree/main/docs_new

PR authors are responsible for ensuring that after merging, all GitHub Action jobs fully pass. A lot of the time, failures are just flakes and simply re-running the failed jobs will fix it. If re-running failed jobs is attempted, PR authors are responsible for ensuring it passes. See GitHub's docs on re-running failed jobs: https://docs.github.com/en/actions/how-tos/manage-workflow-runs/re-run-workflows-and-jobs#re-running-failed-jobs-in-a-workflow

As a rule of thumb, generally, PR authors should request a review & get a PR approval from the respective companies' CODEOWNERS before requesting a review from core maintainers.

If additional help is needed, PR authors can reach out to core maintainers over Slack.

---

感谢你的贡献！对于 vLLM 与 SGLang，请确保你的 recipe 与官方 vLLM recipes 和/或 SGLang cookbook 保持一致

• https://docs.sglang.io/cookbook/intro
• https://recipes.vllm.ai/

如果不一致，请先创建一个 PR，之后我们才能将你的单节点 PR 合并到 master 分支。让我们确保文档保持一流水准，使整个 ML 社区都能从你的辛勤工作中受益！谢谢

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[claude]

LGTM — config-only search-space restructure with matching perf-changelog entry.

Extended reasoning...

Overview

Restructures the aggregate dsr1-fp4-b200-sglang search space in .github/configs/nvidia-master.yaml into low-latency lanes (TP4/EP1 for low concurrency, TP4/EP4 for higher concurrency, with DP-attention on the 8k/1k higher-concurrency lane), drops the TP8/EP8 single-concurrency points, and adds a corresponding perf-changelog.yaml entry linking this PR.

Security risks

None. This is a benchmark search-space YAML change; no code paths, secrets, auth, or permissions are touched.

Level of scrutiny

Low. This is a config-only change to a per-recipe search space. The referenced benchmark script benchmarks/single_node/fixed_seq_len/dsr1_fp4_b200.sh already parameterizes TP, EP_SIZE, and DP_ATTENTION via env vars and gates DP-attention behavior on DP_ATTENTION=true, so the new TP4/EP1 and TP4/EP4+DP-attn lanes are already fully supported without any script changes.

Other factors

No bugs were flagged by the bug hunting system. The changelog entry accurately describes the diff (1k/1k and 8k/1k lane restructuring, drop of TP8/EP8 c1 points) and links back to PR #1975. Concurrency ranges are contiguous (c1–c32 then c64–c256) with no overlap.

[github-actions]

see unofficial run visualizer at https://inferencex.semianalysis.com/inference?unofficialRun=28552491287
see unofficial run visualizer at https://inferencex.semianalysis.com/evaluation?unofficialRun=28552491287

[github-actions]

see unofficial run visualizer at https://inferencex.semianalysis.com/inference?unofficialRun=28554749907
see unofficial run visualizer at https://inferencex.semianalysis.com/evaluation?unofficialRun=28554749907

[github-actions]

see unofficial run visualizer at https://inferencex.semianalysis.com/inference?unofficialRun=28554749907
see unofficial run visualizer at https://inferencex.semianalysis.com/evaluation?unofficialRun=28554749907

[Ankur-singh]

/reuse-sweep-run

[Ankur-singh]

As a PR reviewer and CODEOWNER, I have reviewed this and have:

• Verified that as of the moment of typing this, this is the latest version of PR_REVIEW_CHECKLIST.md
• Verified that the general code quality meets the InferenceX standard and does not make the code quality any worse.
• Verified that this PR has passed PR validation. Please link to GitHub Action workflow that shows this. Link
• Verified that this PR passes evals. Please link to GitHub Action workflow that shows this. Link
• Verified that speculative decoding PRs uses chat templates to align the AL distribution to real world
• If an company claims that they support vLLM/SGLang as first class LLM inference engines on their hardware, I have have verified that the respective vLLM/SGLang submission has been made before additional frameworks (TRT-LLM, ATOM, etc.). The only exceptions are for new hardware, such as MI455X UALoE72, Vera Rubin NVL72, Rubin NVL8, etc., and for new model architectures where there is an actual reason why vLLM/SGLang does not fundamentally support them yet.
• Verified that the single-node recipes are similar to the official vLLM recipes and/or theSGLang cookbook:
  • If they are not, I have verified that a PR has been opened in vLLM recipe repo or SGLang repo and linked it below in the additional detail section:
• If any of the above criteria cannot reasonably be satisfied, I have provided additional reasoning below.

Additional detail section:

• Not a speculative-decoding config — no MTP/EAGLE in this aggregate, so the spec-decoding chat-template requirement is N/A.
• DSR1 FP4 B200 SGLang deployment is documented in the SGLang cookbook (DeepSeek-R1.mdx); the B200 NVFP4 serve command was contributed upstream in Add B200 NVFP4 MTP deployment to DeepSeek-R1 cookbook recipe sgl-project/sglang#29963.

Signed: ankur-singh

[Klaud-Cold]

Verdict: PASS — all checks independently verified at head bcc72e9.

• Check 0 (CODEOWNER): PASS — @ankur-singh is a named owner of .github/configs/nvidia-master.yaml; the other changed files fall under the catch-all only.
• Check 1 (sweep on in-PR commit): PASS — head commit bcc72e9 has all executed single-node 1k1k/8k1k jobs (18 lanes incl. the conc-1 canary) and all 3 eval / jobs green in run 28554749907.
• Check 2 (eval accuracy): PASS — GSM8K em_strict 0.954–0.957 across the three eval lanes, above the dsr1 threshold of 0.91, on this PR's image lmsysorg/sglang:v0.5.12.post1 and model path.
• Check 3 (recipe): PASS — linked recipe sgl-project/sglang#29963 (cookbook DeepSeek-R1.mdx) matches all major args: model nvidia/DeepSeek-R1-0528-FP4-v2 on 4x B200, TP4/EP1 and TP4/EP4+DP-attention lanes (incl. --enable-dp-lm-head), modelopt_fp4, fp8_e4m3 kv-cache, trtllm_mla, flashinfer_trtllm, allreduce fusion. Informational, non-blocking: recipe adds EAGLE MTP flags (this aggregate is spec-none); the 1k1k TP4/EP4 lane runs without the optional DP-attention toggles; --enable-symm-mem (NCCL collectives optimization) is not in the recipe, though its side effect --disable-piecewise-cuda-graph is. Note the recipe PR is still open upstream.
• Check 4 (reuse command): PASS — /reuse-sweep-run posted by Ankur-singh (COLLABORATOR).