[AMD] add dsv4 sglang disagg / 新增 DSv4 SGLang 分离式基准测试#1818
Conversation
billishyahao
requested review from
1am9trash,
seungrokj and
yctseng0211
as code owners
![cursor[bot]](https://avatars.githubusercontent.com/in/1210556?s=60&v=4){kind=small}
There was a problem hiding this comment.
Cursor Bugbot has reviewed your changes and found 1 potential issue.
❌ Bugbot Autofix is OFF. To automatically fix reported issues with cloud agents, enable autofix in the Cursor dashboard.
Reviewed by Cursor Bugbot for commit c22652b. Configure here.
|
see unofficial run visualizer at https://inferencex.semianalysis.com/inference?unofficialRun=27731746053 |
1 similar comment
|
see unofficial run visualizer at https://inferencex.semianalysis.com/inference?unofficialRun=27731746053 |
functionstackx
added
the
all-evals
# Conflicts: # perf-changelog.yaml
|
see unofficial run visualizer at https://inferencex.semianalysis.com/inference?unofficialRun=27731746053 |
| description: | ||
| - "init submission of dsv4 sglang disagg " |
There was a problem hiding this comment.
can u also ur ai agent include descriptions + links of some of the bug fix PRs in here like
|
see unofficial run visualizer at https://inferencex.semianalysis.com/inference?unofficialRun=27893589025 |
|
see unofficial run visualizer at https://inferencex.semianalysis.com/inference?unofficialRun=27896968169 |
|
hi @billishyahao there seems to be an accuracy issues with TP8+TP8. codex has narrowed it down to conc=4, here is the bug report for when u wake up, please take a look https://github.com/SemiAnalysisAI/InferenceX/actions/runs/27896968169/job/82550287079?pr=1818 |
|
see unofficial run visualizer at https://inferencex.semianalysis.com/inference?unofficialRun=28879220277 |
|
see unofficial run visualizer at https://inferencex.semianalysis.com/inference?unofficialRun=28879220277 |
|
see unofficial run visualizer at https://inferencex.semianalysis.com/inference?unofficialRun=28885560673 |
|
see unofficial run visualizer at https://inferencex.semianalysis.com/inference?unofficialRun=28885560673 |
|
see unofficial run visualizer at https://inferencex.semianalysis.com/inference?unofficialRun=28911918964 |
|
/reuse-sweep-run |
There was a problem hiding this comment.
As a PR reviewer and CODEOWNER, I have reviewed this and have:
- Verified that as of the moment of typing this, this is the latest version of PR_REVIEW_CHECKLIST.md
- Verified that the general code quality meets the InferenceX standard and does not make the code quality any worse.
- Verified that this PR has passed PR validation. Please link to GitHub Action workflow that shows this.
- Verified that this PR passes evals. Please link to GitHub Action workflow that shows this.
- Verified that speculative decoding PRs uses chat templates to align the AL distribution to real world
- Verified that the model architecture isn't changed with benchmark hacks like using --hf-overrides to skipping indexer for every x layers on models that don't natively support this. As a general rule, we won't accept optimizations that reduces the number of model architecture FLOPs. Anything that makes that same computation run faster is fair game; FLOPs at lower precisions is fine, given that the config passes private evals. As an general north star princple, we should only use optimizations which is used in production by customers that care about accuracy
- If an company claims that they support vLLM/SGLang as first class LLM inference engines on their hardware, I have verified that the respective vLLM submission made using upstream https://hub.docker.com/u/vllm docker repo, upstream SGLang https://hub.docker.com/u/lmsysorg docker repo. The only exceptions are for new hardware, such as MI455X UALoE72, Vera Rubin NVL72, Rubin NVL8, etc., and for new model architectures where there is an actual reason why vLLM/SGLang does not fundamentally support them yet as supported by vLLM/SGLang community maintainers
- If an company claims that they support vLLM/SGLang as first class upstream in-tree LLM inference engines on their hardware, I have have verified that the respective vLLM/SGLang submission has been made before additional frameworks (TRT-LLM, ATOM, etc.). The only exceptions are for new hardware, such as MI455X UALoE72, Vera Rubin NVL72, Rubin NVL8, etc., and for new model architectures where there is an actual reason why vLLM/SGLang does not fundamentally support them yet.
- Verified that the single-node recipes are similar to the official vLLM recipes and/or theSGLang cookbook:
- If they are not, I have verified that a PR has been opened in vLLM recipe repo or SGLang repo and linked it below in the additional detail section:
- If any of the above criteria cannot reasonably be satisfied, I have provided additional reasoning below.
Additional detail section:
- insert any additional info here
Signed: seungrokj
✅✅✅ Verdict: PASS ✅✅✅✅ Check 0 (CODEOWNER): PASS — Note: the sign-off conversation comment referenced by the gate (id 4921388149) returns 404 (apparently deleted); the identical checklist was verified from |
…opology details Add Chinese: 补充 dsv4 sglang 分离式 changelog 条目的镜像/启动器/拓扑细节
| @@ -38,9 +41,10 @@ | |||
| # cuda_graph_bs_range: str | |||
|
|
|||
| DeepSeek-V3: | |||
There was a problem hiding this comment.
Why are there updates to other models? Shouldn't this PR be self container to v4?
There was a problem hiding this comment.
I split these dp_flags into dp_flags+ep_flags to support dp attention + tp moe. It will not affect the actual behaviour.
| base_flags: "--decode-log-interval 1000 --log-level warning --watchdog-timeout 3600 --load-balance-method round_robin --kv-cache-dtype fp8_e4m3 --attention-backend aiter --disaggregation-transfer-backend mori --moe-dense-tp-size 1" | ||
| mtp_flags: "" | ||
| dp_flags: "--moe-a2a-backend mori --enable-dp-attention --enable-dp-lm-head" | ||
| dp_flags: "--enable-dp-attention --enable-dp-lm-head" |
There was a problem hiding this comment.
yeah preferably can you split these into separate pr please. thank you. shouldnt require re running anything
There was a problem hiding this comment.
This change only made previous legacy model config compatible with latest logic in benchmarks/multi_node/amd_utils/server_sglang.sh. It will not change any behaviours.
8 participants
cc @Duyi-Wang
Note
Medium Risk
Touches shared disagg launch paths (
server_sglang.sh,models.yaml) for all models, not only DSv4; behavior changes when EP is disabled and MoE auto-sizing is partially commented out.Overview
Adds
dsv4-fp4-mi355x-sglang-disaggto the AMD master benchmark matrix (8k/1k, non-MTP) with sweeps over pure TP8, DEP8 (MoRI KV + MoE a2a), and dp-attention + TP-MoE, plus a new workflow runnerdsv4_fp4_mi355x_sglang-disagg.shand a perf-changelog entry.The multi-node harness is extended for DSv4 PD: a
DeepSeek-V4-Problock inmodels.yaml(dsv4 attention backend, mori disagg, prefilldisable_cuda_graph) and matching MoRI/kernel env overrides inenv.sh; the bench client uses--dsv4framing instead of chat templates.server_sglang.sh/models.yamlrefactor MoE CLI soep_flags(mori a2a, deepep, fake dispatch) apply only when EP is on—ep=1stays TP-MoE even with dp-attention—and prefill can honor per-modeldisable_cuda_graph,context_length, and optionalMORI_NUM_MAX_DISPATCH_TOKENS_PER_RANK_*overrides.submit.shthreadsDRY_RUNfor previewing composed launch commands on a real allocation.Reviewed by Cursor Bugbot for commit f56f8de. Bugbot is set up for automated code reviews on this repo. Configure here.
中文说明
在 AMD 主基准测试矩阵中新增
dsv4-fp4-mi355x-sglang-disagg配置（8k/1k，非 MTP），覆盖纯 TP8、DEP8（MoRI KV + MoE a2a）及 dp-attention + TP-MoE 多种扫描点。新增工作流运行器脚本dsv4_fp4_mi355x_sglang-disagg.sh和 perf-changelog 条目。扩展多节点 harness 以支持 DSv4 的 EP 和 MoE 配置。