sync: K3 v7.0.y patchset - #26
Closed
RevySR wants to merge 38 commits into
Closed
Conversation
Populate all pwm device tree nodes for SpacemiT K3 SoC, also documents the pinctrl info which would easily help to enable them in future. Signed-off-by: Yixun Lan <dlan@kernel.org> Link: https://lore.kernel.org/r/20260521-04-k3-pwm-dts-v4-1-04d4de0f2fc8@kernel.org Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
Replace sprintf() with sysfs_emit() in cpu_show_ghostwrite(), which is preferred for formatting sysfs output because it provides safer bounds checking. While the current code only emits fixed strings that fit easily within PAGE_SIZE, use sysfs_emit() to follow secure coding best practices. Signed-off-by: Thorsten Blum <thorsten.blum@linux.dev> Link: https://lore.kernel.org/r/20260510165420.109453-3-thorsten.blum@linux.dev Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
According to SpacemiT updated docs, the PCIe master and slave clock's parent is the pll2_d6 clock, so fix it. Fixes: e371a77 ("clk: spacemit: k3: add the clock tree") Signed-off-by: Yixun Lan <dlan@kernel.org> Link: https://lore.kernel.org/r/20260511-06-pci-clk-fix-v2-1-c9a5e563bab3@kernel.org Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
The offset of PCIe Clock CTRL register for port B and C controller was wrongly swapped, correct it here. Fixes: 091d19c ("clk: spacemit: k3: extract common header") Signed-off-by: Yixun Lan <dlan@kernel.org> Link: https://lore.kernel.org/r/20260511-06-pci-clk-fix-v2-2-c9a5e563bab3@kernel.org Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
Add clock IDs of PCIe DBI (Data Bus Interface) clock. Signed-off-by: Yixun Lan <dlan@kernel.org> Link: https://lore.kernel.org/r/20260511-06-pci-clk-fix-v2-3-c9a5e563bab3@kernel.org Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
Add PCIe DBI (Data Bus Interface) clock which was missing, This will support PCIe driver to explicitly request and enable all clocks that needed. Signed-off-by: Yixun Lan <dlan@kernel.org> Link: https://lore.kernel.org/r/20260511-06-pci-clk-fix-v2-4-c9a5e563bab3@kernel.org Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
The SpacemiT I2C controller's SCL (Serial Clock Line) frequency for master mode operations is determined by the ILCR (I2C Load Count Register). Previously, the driver relied on the hardware's reset default values for this register. The hardware's default ILCR values (SLV=0x156, FLV=0x5d) yield SCL frequencies lower than intended. For example, with the default 31.5 MHz input clock, these default settings result in an SCL frequency of approximately 93 kHz (standard mode) when targeting 100 kHz, and approximately 338 kHz (fast mode) when targeting 400 kHz. These frequencies are below the 100 kHz/400 kHz nominal speeds. This patch integrates the SCL frequency management into the Common Clock Framework (CCF). Specifically, the ILCR register, which acts as a frequency divider for the SCL clock, is now registered as a managed clock (scl_clk) within the CCF. The actual hardware timing formulas are: - standard mode: SCL = FCLK / (2 * SLV + 8) - fast mode: SCL = FCLK / (2 * FLV + 10) These formulas are only valid when the IWCR (Wait Count Register) is programmed to 0x142A, a value specified by the I2C IP designer. The driver now initializes IWCR to this value during controller init. Reviewed-by: Yixun Lan <dlan@gentoo.org> Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com> Link: https://lore.kernel.org/r/20260508-k1-i2c-ilcr-v7-1-8c2dde5c3ed5@linux.spacemit.com Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
…s absent The clock-frequency property is optional according to the DT binding. Do not emit a warning when the property is missing and fall back to the default frequency instead. Reviewed-by: Alex Elder <elder@riscstar.com> Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com> Link: https://lore.kernel.org/r/20260508-k1-i2c-ilcr-v7-2-8c2dde5c3ed5@linux.spacemit.com Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
The BeagleV-Ahead board uses an AP6203BM WiFi chip from AMPAK Technology Inc. connected to SDIO1. The chip is compatible to the broadcom wireless driver. The AP6203BM is a dual-band 2.4GHz/5GHz Wi-Fi 4 (802.11a/b/g/n) and Bluetooth 5.4 module. Bluetooth is not enabled by this patch. Signed-off-by: Thomas Gerner <thomas.gerner@muenchen-mail.de> Link: https://lore.kernel.org/r/20260514183510.234063-1-thomas.gerner@muenchen-mail.de Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
…3way() The module-sections.c file defines a custom cmp_3way() macro to perform 3-way comparisons during relocation sorting. Instead of maintaining our own implementation, use the generic cmp_int() macro provided by the already included <linux/sort.h>. This removes redundant code and relies on standard kernel interfaces. Signed-off-by: Florian Schmaus <florian.schmaus@codasip.com> Link: https://lore.kernel.org/r/20260512063231.708256-1-florian.schmaus@codasip.com Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
Currently, add_resource() returns 1 on success, even though its callers only check for negative values. Instead, propagate the insert_resource() result from add_resource() to align with standard kernel return-value conventions (0 on success, negative errno on failure). Use %pR to print the full resource range while at it. Signed-off-by: Thorsten Blum <thorsten.blum@linux.dev> Link: https://lore.kernel.org/r/20260512172034.328405-4-thorsten.blum@linux.dev Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
To reuse the K1 PCIe driver logic for K3 PCIe controller, add device data to handle the K1 specific logic and make room for the incoming logic for K3. Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Link: https://lore.kernel.org/r/20260517014841.254085-2-inochiama@gmail.com Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
The PCIe controller on Spacemit K3 may use multiple PHYs at the same time. The feature is not support by the current driver. So extend the PHY definition to support multiple PHY handles. Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Link: https://lore.kernel.org/r/20260517014841.254085-3-inochiama@gmail.com Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
…le check The IMSIC device on RISC-V based system does not require ID remapping for MSI. So this device only needs "msi-parent" property for IMSIC-based SoC, and the "msi-map" is not a necessary property. Add new condition for MSI handling on IMSIC based SoC. Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20260517014841.254085-4-inochiama@gmail.com Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
… controller Add binding support for the PCIe controller on the SpacemiT K3 SoC. This controller is almost a standard Synopsys DesignWare PCIe IP, with some extra link and reset state control. Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Link: https://lore.kernel.org/r/20260517014841.254085-5-inochiama@gmail.com Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
The PCIe controller on Spacemit K3 is almost a standard Synopsys DesignWare PCIe IP with extra link and reset control. Unlike the PCIe controller on K1, this controller supports external MSI interrupt controller and can use multiple PHYs at the same time. Add driver to support PCIe controller on Spacemit K3 PCIe. Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Link: https://lore.kernel.org/r/20260517014841.254085-6-inochiama@gmail.com Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
…IPI handler The SBI v0.1 SEND_IPI handler iterates over the hart mask and calls kvm_get_vcpu_by_id() to find the target vcpu for each set bit. When a guest provides a hart mask containing bits for non-existent vcpu_ids, kvm_get_vcpu_by_id() returns NULL, which is then unconditionally dereferenced by kvm_riscv_vcpu_set_interrupt(), causing a kernel crash. Fix this by adding a NULL check before dereferencing the return value. If the target vcpu is not found, skip it and continue processing the remaining valid harts. Fixes: a046c2d ("RISC-V: KVM: Reorganize SBI code by moving SBI v0.1 to its own file") Signed-off-by: Jiakai Xu <jiakaiPeanut@gmail.com> Signed-off-by: Jiakai Xu <xujiakai2025@iscas.ac.cn> Assisted-by: OpenClaw:DeepSeek-V3.2 Link: https://lore.kernel.org/r/20260517124414.420919-1-xujiakai2025@iscas.ac.cn Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
According to SpacemiT K3's updated docs, the USB2 ahb reset and USB2 bus clock enable bit was wrongly swapped, the correct one should be: Register : APMU_USB_CLK_RES_CTRL bit[1] : usb2_port_bus_clk_en bit[0] : usb2_port_ahb_rstn Fixes: e371a77 ("clk: spacemit: k3: add the clock tree") Reported-by: Junzhong Pan <panjunzhong@linux.spacemit.com> Signed-off-by: Yixun Lan <dlan@kernel.org> Link: https://lore.kernel.org/r/20260518-06-clk-reset-usb-fix-v1-1-14fc235e692b@kernel.org Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
According to SpacemiT K3's updated docs, the USB2 ahb reset and USB2 bus clock enable bit was wrongly swapped, the correct one should be: Register : APMU_USB_CLK_RES_CTRL bit[1] : usb2_port_bus_clk_en bit[0] : usb2_port_ahb_rstn Fixes: a0e0c2f ("reset: spacemit: k3: Decouple composite reset lines") Reported-by: Junzhong Pan <panjunzhong@linux.spacemit.com> Signed-off-by: Yixun Lan <dlan@kernel.org> Link: https://lore.kernel.org/r/20260518-06-clk-reset-usb-fix-v1-2-14fc235e692b@kernel.org Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
SpacemiT K3 SoC support dual-voltage I/O power domain, while initially configure to 3.3v, and need to access register from APBC space to switch to 1.8v domain. Fix the GMAC0's I/O pins 1.8v switch failure that will result a broken ethernet driver. Fixes: d894457 ("riscv: dts: spacemit: k3: add pinctrl support") Reported-by: Han Gao <gaohan@iscas.ac.cn> Signed-off-by: Yixun Lan <dlan@kernel.org> Link: https://lore.kernel.org/r/20260518-07-dts-pinctrl-io-power-v1-1-abe19c14a726@kernel.org Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
Add the SpacemiT K3 QSPI compatible to the fsl-qspi binding. K3 has its own SoC integration, so board DTs should describe it with a K3-specific compatible instead of reusing the K1 string. Signed-off-by: Zhengyu He <hezhy472013@gmail.com> Signed-off-by: Cody Kang <cody.kang.hk@outlook.com> Link: https://lore.kernel.org/r/20260519-k3-pico-itx-qspi-v1-v1-1-c32afeeaf741@gmail.com Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
K3 uses the FSL QSPI controller with the same programming model as the existing SpacemiT integration, but has its own compatible string. Add the match entry so DTs using the K3 compatible bind to the driver. Signed-off-by: Zhengyu He <hezhy472013@gmail.com> Signed-off-by: Cody Kang <cody.kang.hk@outlook.com> Link: https://lore.kernel.org/r/20260519-k3-pico-itx-qspi-v1-v1-2-c32afeeaf741@gmail.com Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
Describe the K3 QSPI controller and the pin configuration needed by boards. Enable the bus on Pico-ITX because the board wires QSPI to NOR flash powered from the board 1.8 V QSPI rail. Signed-off-by: Zhengyu He <hezhy472013@gmail.com> Signed-off-by: Cody Kang <cody.kang.hk@outlook.com> Link: https://lore.kernel.org/r/20260519-k3-pico-itx-qspi-v1-v1-3-c32afeeaf741@gmail.com Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
spacemit_pin_set_config() looks up the per-pin descriptor with spacemit_get_pin() then checks the wrong variable for failure: const struct spacemit_pin *spin = spacemit_get_pin(pctrl, pin); ... if (!pin) return -EINVAL; reg = spacemit_pin_to_reg(pctrl, spin->pin); pin is an unsigned int pin id, where 0 (GPIO_0 / gmac0_rxdv on K3) is a valid pin, so rejecting it here drops the PAD config write for the first pin of every group. On K3 Pico-ITX the GMAC RGMII group lists pin 0 as its first entry, so its drive-strength / bias configuration was silently ignored. The intended guard is against spacemit_get_pin() returning NULL when the pin id isn't in the SoC's pin table. Check spin instead, which both restores PAD setup for pin 0 and prevents a NULL deref on spin->pin. Fixes: a83c29e ("pinctrl: spacemit: add support for SpacemiT K1 SoC") Link: https://lore.kernel.org/r/20260519164007.122574-1-gaohan@iscas.ac.cn Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
Select ARCH_KEEP_MEMBLOCK unconditionally. kexec requires memblock to be kept after boot to initialize the secondary kernel. Device Tree platforms also need this for kexec support. Link: https://lore.kernel.org/r/20260519165546.123105-1-gaohan@iscas.ac.cn Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
When kexec_file_load places segments with buf_max=ULONG_MAX and top_down=true, they land at the highest available physical addresses. On RISC-V the size of the linear mapping is determined by the active VM mode: SV39 caps the direct map at roughly 128GB, while SV48/SV57 extend the range substantially further. When the installed physical memory exceeds the direct map size of the active mode, top-down placement puts DTB/initrd at physical addresses outside the linearly mapped region. The kexec'd kernel cannot reach them during early boot, triggering a page fault at memcmp in start_kernel. Fix by constraining buf_max to PFN_PHYS(max_low_pfn), which reflects the runtime direct map boundary for the active VM mode (SV39/SV48/ SV57). This keeps all kexec segments within the linearly mapped region while preserving the upstream top_down allocation strategy. Link: https://lore.kernel.org/r/20260519170641.123517-1-gaohan@iscas.ac.cn Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
The SpacemiT K3 CoM260-IFX board combines a 69.6 × 45 mm compute module with a reference carrier board. The module integrates up to 32GB LPDDR5 memory, UFS storage, Micro SD card slot and includes interfaces such as dual MIPI CSI-2 connectors, M.2 expansion, USB 3.0, Gigabit Ethernet, DisplayPort, and a 40-pin expansion header. The carrier board is intended as a general-purpose development platform for CoM260 module and exposes interfaces for all of storage, display, networking, and camera connectivity. Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Yixun Lan <dlan@kernel.org> Link: https://lore.kernel.org/r/20260520-02-k3-com260-ifx-v2-1-d55095457cf0@kernel.org Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
The K3 CoM260-IFX board combine with one 260 pins "Gold Finger" computer module with a carrier board. The module integrates the K3 SoC, LPDDR5, UFS storage, Gigabit Ethernet, Micro SD card, PMIC Chip. The board offers a comprehensive array of interfaces, including MIPI-DSI, MIPI-CSI, DisplayPort, SDIO, SPI, I2S, I2C, CAN-FD, PWM, UART, USB, PCIe, and GMAC. Add initial support for enabling Serial UART and ethernet. Signed-off-by: Yixun Lan <dlan@kernel.org> Link: https://lore.kernel.org/r/20260520-02-k3-com260-ifx-v2-2-d55095457cf0@kernel.org Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
FROM: spacemit-com@6f15788 The USB2.0 controller on Pico-ITX board connnect to a Terminus FE1.1 Hub which fully USB2.0 protocol compliant and provides 4 ports. Signed-off-by: Yixun Lan <dlan@kernel.org> Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
FROM: spacemit-com/linux-6.18@9168f7e Change-Id: I040d597ee246777767f7be747fa9202154524538 [ Vivian: Rebase and move check into enter_vector_usercopy ] Signed-off-by: Vivian Wang <wangruikang@iscas.ac.cn> Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
The USB3/PCIe comb PHY on the K3 is a complex PHY group that can provide multiple phy for both PCIe and USB controller. Its mux configuration is controlled by the APMU syscon device. Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
The comb PHY on K3 requires to configure a syscon device for the right mux configuration. And it requires calibration before any usage. Add USB3/PCIe comb PHY driver for Spacemit K3. Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
Add all USB device node to the Spacemit K3. Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
Add all PCIe device node for Spacemit K3. Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
The SpacemiT K3 chip's root complex needs to be listed in the allowlist of rtw89 driver to allow 36-bit DMA. Add the vendor and device IDs to pci_ids.h header file. Signed-off-by: Icenowy Zheng <uwu@icenowy.me> Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
The SpacemiT K3 platform has no system memory in the 32-bit address space, and it's verified that the chip works well with 36-bit DMA of RTL8852BE. Add it to the 36-bit DMA allowlist of rtw89_pci. Signed-off-by: Icenowy Zheng <uwu@icenowy.me> Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
The dynamic speed switch functionality seems to be broken on SpacemiT K3, and leads to frequent GPU crashes at least with Polaris GPUs. Disable dynamic speed switch on this platform. Signed-off-by: Icenowy Zheng <uwu@icenowy.me> Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
FROM: RVCK-Project/rvck#213 community inclusion category: bugfix bugzilla: RVCK-Project/rvck#212 -------------------------------- The hdma clk is used by some component of CCI bus, it should be keep always on, regardless of whether hdma enabled. The rcpu clk should be always on because it is running backround. Signed-off-by: Zhang Meng <zhangmeng.kevin@spacemit.com> Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
|
Queued for |
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
11 participants
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
No description provided.